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Title: WiMAX與超寬頻之低雜訊放大器設計
Design of WiMAX and Ultra-Wideband
Authors: 林冠廷
Contributors: NTOU:Department of Electrical Engineering
Keywords: 超寬頻;低雜訊放大器
Date: 2010
Issue Date: 2011-06-22T09:04:36Z
Abstract: 隨著無線傳輸技術的演進,使得無線相關應用產品在人們的生活中日益重要,現今為了滿足龐大的資料傳輸所需頻寬與傳輸速度,擁有多頻帶接收能力的寬頻無線存取(Broadband Wireless Access, BWA)技術也就因應而生。因此本論文以TSMC 0.18μm 1P6M CMOS 製程,針對BWA技術分別在於WiMAX與UWB頻段研製了三個低雜訊放大器。 在WiMXA頻段中,製作了一個使用MOS開關切換於2.5GHz和3.5GHz的低電壓雙頻段低雜訊放大器,此晶片量測結果,頻率偏移為3GHz與3.5GHz,S11與S22皆有小於-14dB的表現,但增益降為9.16dB與9.61dB,雜訊則增加至5.9dB、5.8dB,三階截斷點則分別在-5dB與-0.5dB,其晶片面積為1.03mm2。 在UWB應用中,本論文用了兩種輸入架構,分別為LC帶通濾波器與共源極電阻回授作為輸入端。在第一部份中使用了電源再利用(current-reused)技術來降低對功率的消耗,並完成此高線性超寬頻電路,其S11與S22皆有小於-10dB的表現,增益為9.62dB至12.21dB,增益變動為2.6dB,雜訊為3.3dB至4.1dB之間,三階截斷點則為0.6dB,功率消耗為12.39mW,其晶片面積為0.99mm2。在第二部份中使用了電阻回授反相器(resistive-feedback inverter)技術來增加輸入匹配頻寬,並且只用到三顆電感,對面積的使用更是大為減少,其S11與S22皆有小於-10dB的表現,增益為15.2dB至16.6dB,增益變動為1.4dB,雜訊為2.7dB至4.7dB之間,三階截斷點則為-7dB,功率消耗為18.7mW,其晶片面積為0.46mm2。
With the evolution of wireless transmission technology, the wireless application products are more and more important in people’s lives. Nowadays, to meet the requirement of bandwidth and transmitting velocity for tremendous data transfer, the Broadband Wireless Access (BWA) technology with multi-band access ability is born to application. Therefore, this thesis points on BWA technology especially in WiMAX and UWB bands to implement three low-noise amplifiers in TSMC 0.18μm 1P6M CMOS process. In WiMAX band, we implement a 2.5GHz and 3.5GHz dual-band low-noise amplifier with a MOS switch. The chip measurement results show that the frequency offset to 3GHz and 3.5GHz. The performance of S11 and S22 are less than -14dB, but the gain is reduced to 9.16dB and 9.61dB, respectively. The noise figure is increased to 5.9dB and 5.8dB, and IIP3 is -5dB and -0.5dB, respectively. The chip area is 1.03mm2 In UWB applications, this thesis uses two input structures that are LC bandpass filter and common source resistor feedback. In the first part of the research, the current-reused technique is used to reduce power consumption, and to achieve high linearity and ultra wide bandwidth. The S11 and S22 are less than -10dB. The gain is between 9.62dB and 12.21dB with gain change of 2.6dB. The noise figure is from 3.3dB to 4.1dB. The IIP3 is 0.6dB and the power consumption is 12.39mW. The chip area is 0.99mm2. In the second part of research, the resistive feedback inverter technology is used to increase input matching of bandwidth. With only used of three inductors, the area of chip is greatly reduced. The S11 and S22 are less than -10dB. The gain is between 15.2dB and 16.6dB with gain change of 1.4dB. The noise figure is from 2.7dB to 4.7dB. The third-order intercept point is -7dB and the power consumption is 18.7mW. The chip area is 0.46mm2.
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