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Title: 5.2GHz CMOS非整數型頻率合成器之設計
5.2GHz CMOS Fractional-N Frequency Synthesizer
Authors: Wu-Chuan Cheng
Contributors: NTOU:Department of Electrical Engineering
Keywords: 頻率合成器
Frequency Synthesizer
Date: 2004
Issue Date: 2011-06-22T08:52:36Z
Abstract: 本論文提出一個工作在5GHz頻帶上的分數頻率合成器。整數型頻率合成器無法兼顧頻率解析度與鎖頻時間,而分數頻率合成器無上述問題,但會有分數突波產生,其分數突波可由雜訊整形技術消除。本分數頻率合成器包含相位頻率偵測器、電荷泵浦、迴路濾波器、電壓控制振盪器、除頻器、和差調變器。除頻器係使用注入鎖定除頻器當前置除頻器以減少功率消耗,可程式除頻器當多模除頻器。迴路濾波器為二階被動低通濾波器。和差調變器為MASH 1-1-1架構。電壓控制振盪器為LC振盪器,其在1MHz頻率偏移處的相位雜訊為-116dBc/Hz,可調頻率範圍為4.91GHz至5.38GHz。我們使用台灣積體電路製造公司0.18微米CMOS製程設計鎖相迴路,本分數頻率合成器解析度為27KHz,鎖定時間為8微秒。
A 5GHz CMOS fractional-N frequency synthesizer is designed in this thesis. Usually, it is very difficult to reach high frequency resolution and short locking time at the same time for traditional integer-N frequency synthesizer. While fractional-N frequency synthesis allows a PLL to have finer frequency resolution than reference frequency. But it suffers from fractional supers. These fractional spurs can be reduced and suppressed with a delta-sigma modulator technology. This synthesizer is composed of a phase/frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, frequency dividers and a delta-sigma modulator. The frequency dividers are composed of an injection-locked frequency divider and a programmable divider. The loop filter is a second-order passive filter. The delta-sigma modulator is MASH 1-1-1 architecture. The VCO exhibits a phase noise of -116dBc/Hz at 1MHz offset frequency and an output frequency ranges from 4.91GHz to 5.38GHz. TSMC 0.18um CMOS process is used for this frequency synthesizer design and simulation. The frequency resolution of this fractional-N frequency synthesizer is 27KHz and the locking time is 8 us.
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