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Please use this identifier to cite or link to this item: http://ntour.ntou.edu.tw:8080/ir/handle/987654321/49847

Title: 基於巨量多輸入多輸出系統之快速分群符元偵測法與硬體設計
Fast Group Symbol Detection Schemes and Hardware Design for Massive MIMOs
Authors: Chen, Bo-Sing
陳柏興
Contributors: NTOU:Department of Electrical Engineering
國立臺灣海洋大學:電機工程學系
Keywords: 垂直貝爾分層空時偵測器;空時方塊碼;巨量多輸入多輸出系統;最小均方差;硬體實現
V-BLAST;TBC;massive MIMO;MMSE;hardware implementation
Date: 2017
Issue Date: 2018-08-22T07:13:09Z
Abstract: 在本論文中,我們先針對巨量多輸入多輸出系統提出兩個快速分群偵測法,首先我們先決定每一群的大小G(例如,G=2或G=3),然後進行一群一群的遞迴運算,得到每一群的最小均方差(Minimummeansquareerror,MMSE)偵測器以做為符元偵測使用,且採用遞迴的方式來計算出輔助矩陣作為計算MMSE偵測器之協助,如此可避免直接運算MMSE偵測器,進而降低運算複雜度。有了這些輔助矩陣後,每一群的估測符元即可透過遞迴運算一群一群的估測出來。不僅如此,為了同時接收到空間多樣性與空間多工增益,我們將上述兩個演算法進行延伸,且提出對應的巨量G-STBC多輸入多輸出系統之快速偵測法。最後透過MATLAB模擬與效能分析證實了快速偵測法的效能確實可以十分接近傳統垂直貝爾分層空時偵測器,並且能降低大量的運算複雜度。 為了測試硬體實現,我們更將其中一個名為FGD-B的快速偵測法進行硬體設計。硬體設計的過程中,我們先在巨量多輸入多輸出系統中挑選傳送天線M=24與接收天線N=100,且採用Verilog硬體描述語言進行編碼。其中硬體的模組包含串列輸入並列輸出(Serial-In/Parallel-Out,SIPO)移位暫存器、運算單元與控制器,且在運算單元中,我們僅使用到1個除法器與2個乘法器。最後硬體模擬的結果確實和MATLAB的結果十分相近,且和現存的方法進行比較,我們所提出的FGD-B架構亦較為簡單且可行。
In the thesis we present two fast group detection schemes for massive MIMO systems. First, a number G, (e.g., G = 2 or G = 3) is chosen as the size of each group. Then, the proposed schemes recursively compute the MMSE detectors group by group to facilitate symbol detection. Specifically, to avoid the huge complexity required to directly compute the MMSE detectors, the schemes recursively find the corresponding assistant matrices to help determine the groups and calculate the MMSE detectors. As a result, the transmitted symbols can be recursively estimated group by group. Furthermore, to concurrently receive the spatial diversity and spatial multiplexing gains, we also extend the two above schemes and propose a corresponding fast detection method for massive G-STBC MIMO systems. Our MATLAB simulation results and complexity analysis show that the proposed schemes can achieve a performance close to that of the conventional V-BLAST algorithm with a significant saving in computational complexity. To test the physical implementation, we further carry out the hardware design of the proposed schemes. For this, one of the above proposed schemes, namely FGD-B, is coded with Verilog HDL(Hardware Description Language) for the massive MIMO system with M = 24 transmit antennas and N = 100 receive antennas. The hardware modules we designed include SIPO (Serial-In/Parallel-Out) shift registers, a computing unit and a controller. Specially, the hardware computing unit only contains one Divider and two Multiplier. Finally, the hardware simulation results achieve almost the same as the above MATLAB's. In addition, compared to the existing method, the proposed hardware architecture for FGD-B is simple and feasible.
URI: http://ethesys.lib.ntou.edu.tw/cgi-bin/gs32/gsweb.cgi?o=dstdcdr&s=G0010453012.id
http://ntour.ntou.edu.tw:8080/ir/handle/987654321/49847
Appears in Collections:[電機工程學系] 博碩士論文

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