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Please use this identifier to cite or link to this item: http://ntour.ntou.edu.tw:8080/ir/handle/987654321/49795

Title: 應用於Ku頻段通訊系統之低功耗射頻接收機前端積體電路設計與分析
Design and Analysis of Low Power RF Receiver Front-end Integrated Circuits for Ku-band Communication System
Authors: Chang, Chun-I
張君毅
Contributors: NTOU:Department of Electrical Engineering
國立臺灣海洋大學:電機工程學系
Keywords: 電壓控制振盪器;低雜訊放大器;混頻器
voltage-controlled oscillator;low noise amplifier;mixer
Date: 2017
Issue Date: 2018-08-22T07:11:51Z
Abstract: 本論文設計用於Ku頻段通訊系統之射頻接收機前端電路,其中包括電壓控制振盪器、低雜訊放大器以及混頻器,佈局所用之元件均為TSMC 0.18μm 1P6M CMOS Mixed-Signal模型,並在國家晶片系統設計中心所提供之EDA Cloud雲端平台上以Agilent Advanced Design System (ADS)軟體進行電路模擬。 第一顆晶片為電壓控制振盪器(VCO),使用互補式交叉耦合對架構和轉導提升架構,結合了PMOS與NMOS型式的優點來降低消耗功率。根據模擬結果顯示,相位雜訊在1MHz時為-112.9 dBc/Hz,可調頻率範圍為3.5%,性能指標(FOM)值為-191.1 dBc/Hz,電壓輸入為1.8 V,消耗功率為3.35 mW,晶片面積為0.707*0.682 mm2。 第二顆晶片為低雜訊放大器(LNA),核心電路使用電流再利用式架構來降低消耗功率,並且使用源極退化電感來改善線性度。根據量測結果顯示,操作中心頻率為15 GHz,輸入反射係數為-7 dB,輸出反射係數為-13 dB,增益為0.22 dB,雜訊指數為5.9 dB,IIP3為+3 dBm,在供應電壓為1.8 V時,消耗功率為4.64 mW,晶片面積為0.822*0.754 mm2。 第三顆晶片為混頻器(Mixer),核心電路使用單端平衡式架構,與雙端平衡式相比所需功耗較低,轉導級使用電流注入技術來提高整體轉換增益與抑制雜訊。根據模擬結果顯示,在輸出訊號頻率為15 GHz時,轉換增益為12.8 dB,雜訊指數為16.3 dB,輸入1dB增益壓縮點為-17 dBm,輸入三階截止點為-5 dBm,在供應電壓為1.8 V時,消耗功率為37 mW,晶片面積為1.01*0.71 mm2。
In this thesis, RF receiver front-end circuits for Ku-band communication system are presented, which consist of a voltage-controlled oscillator, a low noise amplifier, and a mixer. The circuits have been designed by TSMC 0.18 um 1P6M CMOS Mixed-Signal model, and simulated in the Agilent Advanced Design System (ADS) software on EDA Cloud service provided by National Chip Implementation Center. The first chip is a voltage-controlled oscillator (VCO), designed with complementary cross-coupled pair architecture and gm boosting technique that combine the advantages of PMOS and NMOS to reduce power consumption. According to the simulation results, the phase noise is -112.9 dBc/Hz at 1MHz offset, the tuning range is 3.5%, the figure of merit (FOM) is -191.1 dBc/Hz, and the power consumption is 3.35 mW at 1.8V power supply. The chip size is 0.707*0.682 mm2. The second chip is a low noise amplifier (LNA). The core uses the current-reuse architecture to reduce power consumption and adopts inductive source degeneration to improve linearity. The measurement results of the LNA show that the operating frequency center is 15 GHz, the input reflection is -7 dB, the output reflection is -13 dB, the power gain is 0.22 dB, the noise figure is 5.9 dB, the IIP3 is +3 dBm. The power consumption is 4.64 mW at 1.8V supply voltage. The chip size is 0.822*0.754 mm2. The third chip is a mixer (Mixer). The core uses the single balanced architecture, instead of the double balanced one to achieve low power consumption. In the transconductance stage, we uses a current bleeding technique to improve the overall conversion gain and reduce noise. The simulation results of this Mixer show that the conversion gain is 12.8 dB, the noise figure is 16.3 dB, the P1dB is -17 dBm, the IIP3 is -5 dBm at output frequency of 15 GHz. The power consumption is 37 mW at a supply voltage of 1.8 V, and the chip area is 1.01*0.71 mm2.
URI: http://ethesys.lib.ntou.edu.tw/cgi-bin/gs32/gsweb.cgi?o=dstdcdr&s=G0010353008.id
http://ntour.ntou.edu.tw:8080/ir/handle/987654321/49795
Appears in Collections:[電機工程學系] 博碩士論文

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