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Please use this identifier to cite or link to this item: http://ntour.ntou.edu.tw:8080/ir/handle/987654321/49753

Title: 以FPGA實現數位化正子斷層造影儀之訊號處理與控制系統
FPGA-Based Signal Processing And Control System For Digital Positron Emission Tomography
Authors: Lee, Chun-Wei
李俊緯
Contributors: NTOU:Department of Electrical Engineering
國立臺灣海洋大學:電機工程學系
Keywords: 數位化正子斷層造影儀
digital positron emission tomography;Pulse Shape Discrimination;Depth of Interaction
Date: 2016
Issue Date: 2018-08-22T07:10:59Z
Abstract:   本論文的主要目的在於實現數位化正子斷層造影儀(Positron Emission Tomography,簡稱PET)之訊號處理與控制系統,並針對決定γ射線射入晶體之深度資訊(Depth of Interaction, 簡稱DOI)的兩種傳統類比式判別方法,進行數位化實現與分析。   訊號處理系統包含數位波形擷取模組、位置資訊計算模組、能量資訊計算模組和用於DOI計算之晶體判別模組。控制系統包含時間符合之資訊判別與編碼模組、資料合併模組和資料傳輸模組。整個系統以Verilog HDL語言實現於Terasic 公司開發的的Altera DE3 FPGA 發展平台。   此外在DOI資訊之晶體判別的部分,本論文將兩種傳統類比式Pulse Shape Discrimination(簡稱PSD)方法進行數位化與分析,分別為Rise Time Discrimination (簡稱RTD)和Delayed Charge Integration (簡稱DCI)。在經過實驗與數據分析後,發現DCI方法的成功辨識率較RTD高。   整合後之訊號處理與控制系統的Input Siganl Hold Time、Dead Time和Delay Time 分別為,符合一般正子系統之需求。
  The main objective of this research is to design and implement the signal processing and control system of digital positron emission tomography. Two traditional discrimination methods for ray Depth of Interaction (DOI) determination have been implemented in digital scheme and their performances were analyzed and compared.   The signal processing system consists of digital pulse capturing module, position estimation module, energy calculating module and scintillator discrimination module for DOI estimation. The control system consists of time coincidence and data formatting module, data combining module, and data transformation module. The whole system is designed and implemented on DE3 field-programmable gate array (FPGA) platform developed by Terasic Company, in which the Verilog hardware description language (HDL) is used for FPGA programming.   In DOI determination, we analysised and compared two Pulse Shape Discrimination (PSD) methods for LYSO and LSO scintillators in phoswich assemblies, which are Rise Time Discrimination (RTD) and Delayed Charge Integration (DCI). According to the simulation and hardware experiment results, it is clear that DCI method has better performance than the RTD method.   After the integration of the signal processing system and the control system, the system testing results show that the input signal hold time, dead time, and delay time of the whole digital system are 20 ns, 1.18 μs, and 1.34 μs, respectively.
URI: http://ethesys.lib.ntou.edu.tw/cgi-bin/gs32/gsweb.cgi?o=dstdcdr&s=G0010353042.id
http://ntour.ntou.edu.tw:8080/ir/handle/987654321/49753
Appears in Collections:[電機工程學系] 博碩士論文

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