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Analysis and suppression of common mode noise and Electrostatic discharge occurring at the High-Speed Communication Interface
|Authors: ||Wu, Ming-Feng|
|Contributors: ||NTOU:Department of Electrical Engineering|
Commom mode noise;ElectroStatic Discharge;Electromagnetic Compatibility;Electric Magnetic Interruption
|Issue Date: ||2018-08-22T07:10:30Z
|Abstract: ||本論文研究主機板上之高速電路通訊介面所發生的對地共模傳導雜訊之抑制對策與USB3.1積體電路(Integrated Circuit,IC)內部針對靜電耐受性的提升與防制。由於主機板上之共模干擾電流會藉由電纜或電源的直接傳導方式去影響周邊電子設備導致其誤動作或性能失效，因此在第一部份研究10 GBase-T高速通訊介面的共模雜訊抑制，依據著CNS13438之法規來做通訊介面之共模擾動干擾之量測，並利用共模扼流線圈與Bob-Smith電路的共模抑制對策，使其主機板內部減少對地的共模雜訊電流進而減少主機板對外在環境的傳導干擾影響程度。 第二部份的研究為如何提升主機板內部的高速傳輸晶片層級對於靜電的衝擊，依據法規IEC61000-4-2使用靜電槍來完成此項測試，並藉由TLP傳輸脈衝量測判斷出晶片與外部之防護元件TVS之箝制電壓, 藉由低電壓與低容值的靜電防護元件選用以及針對信號眼狀圖的量測來提升並確保晶片之靜電耐受度與高速信號因防護元件的寄生容值對信號的上升時間與下降時間及抖動現象等影響，進而判斷信號是否有符合眼狀圖的法規規範值。|
This thesis deals with two subject matters that commonly associate with the performance of high speed communication (HSC) device. The first is on the existence of common mode noise (CMN) occurring at the HSC interface due to non-ideal grounding. The second is on the analysis and upgrade on electrostatic discharge (ESD) tolerance of the integrated circuit of USB3.1. The HSC interfacial CMN induced interference may propagate along the connecting cable or directly transmitted via the power source to influence the proper operation of the surrounding electronic devices. The interference may lead to malfunction or failure of the electronic equipment. Therefore in the first part of our investigative work, we analyzed the CMN occurring at a 10 GBase-T HSC interface and implemented various means to suppress such interferences. The measurement of the interfacial CMN of the telecommunication interface is in accordance with the protocol CNS13438 standard’s measurement method of the impedance stabilization networks. The methodologies implemented consisted of the use of high frequency noise suppression electronics device such as the common mode choke and Bob-Smith Circuit to inhibit the HSC interfacial CMN current to the GND’s loop occurring from the Motherboard. We have demonstrated that the applied procedure can reduce the Motherboard internal CMN current, thereby minimizing the conduction emission interference impact of the Motherboard on the peripheral environment. Next, the issue of ESD tolerance of the integrated circuit of USB3.1.is addressed. The measurement is in accordance with the protocol IEC61000-4-2 using ESD gun to complete this investigation and utilizing the transmission line pulsing system to measure the clamping voltage between the integrated circuit of USB3.1 and the external protective device which consists of a transient-voltage-suppression (TVS) diode. The ESD suppressing TVS diode can affect the signal integrity of the system via influencing the High-Speed signal waveform rise time, fall time, and jitters. Through adopting TVS diode with low clamping voltage and capacitance values as the ESD protective measure and utilizing the USB3.1 electrical transmitter compliance testing, we have ascertained the improvement of ESD immunity and signal integrity of the integrated circuit of USB3.1.
|Appears in Collections:||[電機工程學系] 博碩士論文|
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