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Please use this identifier to cite or link to this item: http://ntour.ntou.edu.tw:8080/ir/handle/987654321/49699

Title: 5G Wi-Fi之CMOS射頻接收機前端積體電路設計
Authors: Lee, Yuan-Han
李元瀚
Contributors: NTOU:Department of Electrical Engineering
國立臺灣海洋大學:電機工程學系
Keywords: 電壓控制振盪器;低雜訊放大器;混頻器
voltage-controlled oscillator;low noise amplifier;mixer
Date: 2015
Issue Date: 2018-08-22T07:10:09Z
Abstract: 本論文設計用於IEEE 802.11ac頻帶內之射頻接收機前端電路,其中包括電壓控制振盪器、低雜訊放大器以及混頻器,並且以整合為接收機為目的,佈局所用之元件均為TSMC 0.18μm 1P6M CMOS Mixed-Signal模型,並在國家晶片系統設計中心所提供之EDA Cloud雲端平台上以Agilent Advanced Design System (ADS)軟體進行電路模擬。 第一顆晶片為電壓控制振盪器(VCO),使用Q值提升架構以及基底偏壓技術來設計電路,並期望其可調頻率範圍能包含整個IEEE 802.11ac的操作頻段。量測結果顯示,振盪頻率為5.38-6.30 GHz,可調頻率範圍達16.7%,在振盪頻率為5.3GHz時,輸出功率為-9.7dBm,相位雜訊在1MHz的偏移頻率時為-110dBc/Hz,在供應電壓為1.4V時,消耗功率為10.08mW,晶片面積為0.43mm2。 第二顆晶片為低雜訊放大器(LNA),核心電路使用電流再利用式架構來降低消耗功率,而第二級使用折疊疊接的架構提高電路的增益且不壓縮頭部電壓。量測結果顯示,操作中心頻率為6.465GHz,輸入反射係數為-23dB,輸出反射係數為-10dB,增益為12.2dB,雜訊指數為3.88dB,IIP3為-2dBm,在供應電壓為1.4V時,消耗功率為28.2mW,晶片面積為0.93 mm2。 第三顆晶片為混頻器(Mixer),核心電路使用雙端平衡式架構,轉導級使用改良式二級共源極架構搭配源極衰減電阻,提高轉導值與降低功率消耗,負載級則是使用共模回授架構來提高轉換益。模擬結果顯示,在輸出訊號頻率為5.5GHz時,轉換增益為6.5dB,雜訊指數為11dB,輸入1dB增益壓縮點為-17dBm,輸入三階截止點為-11dBm,在供應電壓為1.4V時,消耗功率為4.51mW,晶片面積為1.4 mm2。
In this thesis, RF receiver front-end circuits for IEEE 802.11ac are presented and dedicated to a system on a chip, which consist of a voltage-controlled oscillator, a low noise amplifier, and a mixer. The circuits are designed by TSMC 0.18 um 1P6M CMOS Mixed-Signal model, and simulated in the Agilent Advanced Design System (ADS) software on EDA Cloud service provided by National Chip Implementation Center. The first chip is a voltage-controlled oscillator (VCO), designed with Q-enhancement architecture and body-biasing technique, and its tuning range is expected to cover the entire operating band of IEEE 802.11ac. The measurement results of the VCO show that the oscillation frequency range is from 5.38 GHz to 6.30 GHz, and the tuning range is 16.7%. The measured output power is -9.7dBm and phase noise is -110dBc/Hz at 1MHz offset from the operation frequency 5.3 GHz. The total power consumption is 10.08mW at a supply voltage of 1.4V, and the chip area is 0.43mm2. The second chip is a low noise amplifier (LNA). The core uses the current-reuse architecture to reduce power consumption, and the second stage is adopted the folded-cascode architecture to increase the gain and not suppress the voltage headroom. The measurement results of the LNA show that the operating frequency center is 6.465 GHz, the input reflection is -23dB, the output reflection is -10dB, the power gain is 12.2dB, the noise figure is 3.88dB, the IIP3 is -2dBm. The power consumption is 28.2mW at 1.4V supply voltage. The chip size is 0.93mm2. The third chip is a mixer of which the core uses the double balanced architecture. In the transconductance stage, it uses a modified two common source architecture with source degeneration resistances to increase the transconductance and reduce power consumption. The load stage adopts the common mode feedback architecture to improve the conversion gain. The simulation results of the LNA show that the conversion gain is 6.5dB, the noise figure is 11dB, the P1dB is -17dBm, the IIP3 is -11dBm at output frequency of 5.5GHz. The power consumption is 4.51mW at a supply voltage of 1.4V, and the chip area is 1.4mm2.
URI: http://ethesys.lib.ntou.edu.tw/cgi-bin/gs32/gsweb.cgi?o=dstdcdr&s=G0010253011.id
http://ntour.ntou.edu.tw:8080/ir/handle/987654321/49699
Appears in Collections:[電機工程學系] 博碩士論文

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