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Please use this identifier to cite or link to this item: http://ntour.ntou.edu.tw:8080/ir/handle/987654321/49600

Title: 一個新的通用型交換方塊之FPGA設計
A New Universal Switch Block for FPGA Design
Authors: Wu, Chang-Tu
吳昌圖
Contributors: NTOU:Department of Electrical Engineering
國立臺灣海洋大學:電機工程學系
Keywords: 現場可程式邏輯陣列;可重組;通用型;繞線;交換方塊;交換網路
Field Programmable Gate Arrays (FPGA);rearrangeable;universal;routing;switch block;switching network
Date: 2014
Issue Date: 2018-08-22T07:09:07Z
Abstract: 本論文係探討設計一個點對點的互連結構,並提出一個簡易型的交換方塊架構,可直接應用於現場可程式邏輯陣列(FPGA)、交換方塊及通信交換網路之設計。我們提出一個新的通用型交換方塊,該架構為四邊形方塊,每一邊有m個端點建構而成,可繞線於所有2-pin的繞線需求。我們有正規的理論分析及廣泛的基準電路繞線能力評估實驗,並與目前著名的FPGA交換方塊,例如不相交交換方塊(Xilinx XC4000型)、Wilton’s交換方塊、Universal交換方塊及本論文所提出的新通用型交換方塊,對其繞線能力作出比較。為了與Chang’s Universal交換方塊有所區分,我們將新的通用型交換方塊命名為Yen’s交換方塊或縮寫為YSB。我們新設計之結構,可重組應用於交換網路之設計,並可適用於多點連接(例如電話網路)。簡易地使用寬度為m #westeur024# m連結四邊形的通用型交換方塊,就可建構實現每一邊分為三個階段對應於單邊的交換網路,以實現點對點的連接需求。除此之外,本論文設計之架構具有細密的分解特性,因此本架構在VLSI佈線上具有高度延展性及規則性,而且此分解特性可以運用在繞線演算法上。
This study explores theories on designing two-point interconnection structures, proposing a simple switch block scheme can be directly applied to field programmable gate arrays (FPGAs), switch block designs, and communications switching networks designs. We present a new universal switch blocks with four sides and m terminals on each side, which is routable for every two-pin net-routing requirement. We also give a formal analysis and extensive benchmark experiments on routability comparisons between today’s most well-known FPGA switch blocks like disjoint switch blocks (Xilinx XC4000 Type), Wilton’s switch blocks, Universal switch blocks, and our universal switch blocks. To distinguish our design from Chang’s switch blocks, we name our universal switch blocks after Yen’s switch blocks, or YSBs for short. We apply the design scheme to rearrangeable switching network designs targeting for applications of connecting multiple terminals (e.g., teleconferencing). Simply using a 4-sided universal switch block with a mm crossbar attached to each side, one can build a three-stage one sided switching network capable of realizing every two-point connection requirement on m-terminals. Besides, due to the fine-grained decomposition property of our design scheme, the new designs are highly scalable and regulation on physical layout and routing algorithm implementations.
URI: http://ethesys.lib.ntou.edu.tw/cgi-bin/gs32/gsweb.cgi?o=dstdcdr&s=G0049943020.id
http://ntour.ntou.edu.tw:8080/ir/handle/987654321/49600
Appears in Collections:[電機工程學系] 博碩士論文

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