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Please use this identifier to cite or link to this item: http://ntour.ntou.edu.tw:8080/ir/handle/987654321/49302

Title: 具有I2C功能之8051微控制器設計與實作
Design and Implementation of 8051 Microcontroller with I2C
Authors: Chung, Chang-Hsien
鍾昌憲
Contributors: NTOU:Department of Computer Science and Engineering
國立臺灣海洋大學:資訊工程學系
Keywords: I2C;系統級封裝;Cell-based;硬體描述語言
I2C;System in Package;Cell-based;HDL
Date: 2015
Issue Date: 2018-08-22T06:56:27Z
Abstract: 隨著資訊產業的快速發展,電子設備與資訊傳遞已經成為人們不可取代的必需品,然而電子產品的應用日趨廣泛,使得各個裝置的連接介面變的十分重要。I2C (Inter Integrated Circuit)串列匯流排以其介面簡單、成本低、可擴展性好,在數位系統中得到了廣泛的應用,成為事實上的標準。本論文中我們設計與實現一個具有I2C功能的8051微控制器,而針對EMC實驗的部分,我們也設計了8051和SRAM的裸晶去實現SiP (System in Package)。此外,我們對於IC-EMC測試平臺特別設計了一個ISP機制。在驗證上,我們使用KEIL C和實驗室團隊製作的8051 IDE Tools產生program ROM檔,最後我們使用Cell-based設計流程來實現具有I2C 功能的8051 MCU,IC內部的結構採用SRAM-Based。具有I2C功能的8051微控制器是使用硬體描述語言(Hardware Description Language,HDL)來實作,晶片的部分是使用TSMC 0.18um製程,核心加上I/O pad的面積大小為1.2 #westeur024# 1.2 mm2,晶片最高工作時脈可達100MHz。
With the rapid development of information technology industry, electronic products and information transmissions are considered a necessity by a lot of people. However, the electronic products are widely available, and it is very important to connect each equipment interface. I2C (Inter Integrated Circuit) serial bus is widely applied in digital system because of its simple interface, low cost and good expansibility. It has been the actual standard. In this thesis, we designed and implementation an 8051 microcontroller with I2C. For EMC experimentation, we also design an SRAM and 8051 bare-die to implement in an SiP (System in Package). Furthermore, we design the ISP mechanism for an IC-EMC testing platform. In the experiment of verification, we used KEIL C and the 8051 IDE Tools to create program ROM file. Finally, we used cell-based design flow to equip the 8051 MCU with I2C functionality with an SRAM-based design for the structure of the IC. The 8051 microcontroller with I2C was implemented by using Hardware Description Language (HDL). The chip is implemented in TSMC 0.18um process. The core size with I/O pad is 1.2 #westeur024# 1.2 mm2. The maximum clock rate can reach 100MHz.
URI: http://ethesys.lib.ntou.edu.tw/cgi-bin/gs32/gsweb.cgi?o=dstdcdr&s=G0010157019.id
http://ntour.ntou.edu.tw:8080/ir/handle/987654321/49302
Appears in Collections:[資訊工程學系] 博碩士論文

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