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Please use this identifier to cite or link to this item: http://ntour.ntou.edu.tw:8080/ir/handle/987654321/46157

Title: Implementation of Chip-Level EMC Strategies in 0.18 µm CMOS Technology
Authors: Yin-Cheng Chang
Ping-Yi Wang
Shawn S. H. Hsu
Mao-Hsu Yen
Yen-Tang Chang
Jian-Li Dong
Ta-Yeh Lin
Da-Chiang Chang
Contributors: 國立臺灣海洋大學:資訊工程學系
NTOU:Department of Computer Science and Engineering
Keywords: integrated circuit (IC);electromagnetic interference (EMI);electromagnetic susceptibility (EMS);slew rate controller;decoupling capacitor
Date: 2017-06
Issue Date: 2018-05-07T02:52:13Z
Publisher: Electromagnetic Compatibility (APEMC), 2017 Asia-Pacific International Symposium on
Abstract: Astract:
Two on-chip electromagnetic compatibility (EMC) solutions realized in the standard 0.18 µm CMOS technology are proposed. A slew rate controller for electromagnetic interference (EMI) reduction is demonstrated by increasing the rise and fall time of signal to lower the harmonic energy on FFT spectrum. Besides, a MOS plus MOM decoupling capacitor for both EMI and electromagnetic susceptibility (EMS) issues is proposed to provide a 17.6 % added capacitance than the conventional decoupling capacitors under the same area. The experiment results prove that the proposed EMC strategies are effective and can be utilized in the chip design with low design complexity.
Relation: pp. 390-392
URI: http://ntour.ntou.edu.tw:8080/ir/handle/987654321/46157
Appears in Collections:[資訊工程學系] 演講及研討會

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