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Please use this identifier to cite or link to this item: http://ntour.ntou.edu.tw:8080/ir/handle/987654321/40315

Title: Area-Efficient 128- to 2048/1536-Point Pipeline FFT Processor for LTE and Mobile WiMAX Systems
Authors: Chu Yu;Mao-Hsu Yen
Contributors: 國立臺灣海洋大學:資訊工程學系
Date: 2014
Issue Date: 2017-01-17T06:21:21Z
Publisher: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Abstract: Abstract
Fast Fourier transform (FFT) is widely used in digital signal processing and telecommunications, particularly in orthogonal frequency division multiplexing systems, to overcome the problems associated with orthogonal subcarriers. This paper presents a novel 128/256/512/1024/1536/2048-point single-path delay feedback (SDF) pipeline FFT processor for long-term evolution and mobile worldwide interoperability for microwave access systems. The proposed design employs a low-cost computation scheme to enable 1536-point FFT, which significantly reduces hardware costs as well as power consumption. In conjunction with the aforementioned 1536-point FFT computation scheme, the proposed design included an efficient three-stage SDF pipeline architecture on which to implement a radix-3 FFT. The new radix-3 SDF pipeline FFT processor simplifies its data flow and is easy to control, and the complexity of the resulting hardware is lower than that of existing structures. This paper also formulated a hardware-sharing mechanism to reduce the memory space requirements of the proposed 1536-point FFT computation scheme. The proposed design was implemented using 90 nm CMOS technology. Postlayout simulation results revealed a die area of approximately mm with power consumption of only 9.3 mW at 40 MHz.
Relation: 23(9)
URI: http://ntour.ntou.edu.tw:8080/ir/handle/987654321/40315
Appears in Collections:[資訊工程學系] 期刊論文

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