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|Title: ||Design and implementation of a single chip FPGA-based coincidence unit for Positron Emission Mammography|
|Authors: ||Tzong-Dar Wu;Chung-Hung Chang;Meei-Ling Jan|
|Issue Date: ||2016-08-03T02:23:05Z
|Abstract: ||Abstract: The design of modern Positron Emission Mammography has been toward to modular, flexible, and compact. The use of Field Programmable Gate Arrays (FPGA) and Digital Signal Processing (DSP) provide enough reprogrammable flexibility and expandability in the evolution of modern PEM scanners. One of the core technologies suited for the FPGA implementation is the detection circuits for coincidence events. In this paper, a compact low dead-time coincidence system for the PEM camera is proposed and implemented on a single FPGA chip. The Pulse-AND logic method is chosen firstly to be realized in the coincidence detection because of its simplicity. The hardware simulation results show that the dead time of our system is less than 15 ns. However, the drawback of the Pulse-And method is sensitive to noise. A new hybrid coincidence approach combining Pulse-And logic and the traditional timing mark methods is also proposed and implemented on a single FPGA chip. The block diagram of the proposed system is shown in Fig.1. By using Pulse-And method for the rough coincidence detection and the timing-mark method for the final coincidence decision, the proposed hybrid system has the advantage of less noise sensitivity, and in the same time, reduce the complexity of the timing mark system. In our simulation, the 16 possible pair combinations of modules are derived from 4 detector modules in coincidence with 4 opposite modules. In order to test the capability of the single chip coincidence system, the possible pair combinations of modules are extended to 144, which derived from 12 detector modules in coincidence with 12 opposite modules. In order to reduce the circuit complexity in the 144 pair combination realization, the grouping and encoding techniques are used to divide the modules into different group before the detection of coincidence. Hardware simulations show that the resource of the FPGA can be reduced and the system dead time can be decreased.|
|Appears in Collections:||[電機工程學系] 期刊論文|
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