English  |  正體中文  |  简体中文  |  Items with full text/Total items : 28611/40649
Visitors : 614545      Online Users : 84
RC Version 4.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Adv. Search

Please use this identifier to cite or link to this item: http://ntour.ntou.edu.tw:8080/ir/handle/987654321/28587

Title: Optimization of Component Placement Scheduling for SMT Assemblies
Authors: Chung Hsien Kuo;M.D. Jeng;J.J. Wing;Tai Hong Wang
Contributors: NTOU:Department of Electrical Engineering
Keywords: Cycle Time Evaluation;Optimal Component Placement Scheduler;Production Modeling;Route Oriented Petri Net;Surface Mount Technology (SMT)
Date: 2006-01
Issue Date: 2011-10-21T02:38:18Z
Publisher: Materials Science Forum
Abstract: Abstract:The surface mounting of electronic component is the major manufacturing technology for the electronic products in the last decade. The surface mounting technology (SMT) is an assembly process that assembles the surface mountable component (SMC) and the printed circuit board (PCB) together. The SMT mounter is an automatic assembly machine that processes the SMT assemblies in terms of the optical positioning and robotic handling. The SMT assembly consists of calibrating printed circuit board (PCB); vacuuming components form feeder stations; compensating the orientation of the vacuumed surface mountable component (SMC); and finally placing SMC chips on the PCB. In order to increase the throughput, the synchronous batch vacuuming of SMC components is designed. In addition, different types of component feeding and mixing in each batch increase the difficulties of finding the best component mounting sequence. In this paper, the optimal component placement scheduler is desired to perform higher assembly performance and to reduce the cycle time. The proposed optimal component placement scheduler is developed based on the rule based heuristic search approach. In addition, to evaluate the cycle time of each heuristic search, the route oriented Petri nets (ROPN) based SMT assembly models are constructed. The optimal component placement scheduler can be further determined in terms of evaluating the ROPN SMT assembly models. Finally, the practical test PCB board data is discussed in this paper.
Relation: 505-507, pp.1123-1128
URI: http://ntour.ntou.edu.tw/handle/987654321/28587
Appears in Collections:[電機工程學系] 期刊論文

Files in This Item:

There are no files associated with this item.

All items in NTOUR are protected by copyright, with all rights reserved.


著作權政策宣告: 本網站之內容為國立臺灣海洋大學所收錄之機構典藏,無償提供學術研究與公眾教育等公益性使用,請合理使用本網站之內容,以尊重著作權人之權益。
網站維護: 海大圖資處 圖書系統組
DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback