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Please use this identifier to cite or link to this item: http://ntour.ntou.edu.tw:8080/ir/handle/987654321/28368

Title: A Low-voltage low-power programmable 5 GHz frequency synthesizer in standard 0.18 µm CMOS process
Authors: M. L. Yeh;W. R. Liou;T. H. Chen;Y. C. Lin
Contributors: 國立臺灣海洋大學:電機工程學系
Keywords: frequency synthesizer;Colpitts;injection locked frequency divider;voltage-controlled oscillator
Date: 2006
Issue Date: 2011-10-21T02:37:18Z
Publisher: International Journal of Electronics
Abstract: abstract:A low-voltage programmable frequency synthesizer with 12.5 mW power consumption is designed for wireless communications. This synthesizer is implemented using Taiwan Semiconductor Manufacture Company (TSMC) 0.18um 1P6M triple-well technology, with an operating voltage of 1.5 volts, and an output frequency range from 4.58GHz to 5.20 GHz. Based on thestructure of phase-locked loop, we developed this fully integrated frequency synthesizer using the phase-locked (PLL) loop structure, consisting of a phase/frequency detector (PFD), a charge pump, a low-pass filter, a voltage-controlled oscillator, and a frequency divider. The PFD is composed of dynamic two-phase master-slave pass-transistor flip-flops. Only single-edge clocks are used to minimize clock skew. To reduce the charge sharing and clock feed-through problems a novel charge pump structure is designed. A three-order low-passfilter is used to filter out the high-frequency alias of charge pump circuit. The voltage-controlled oscillator adopts a novel differential Colpitts oscillator structure to increase the oscillator frequency to 5 GHz. An injection-locked frequency divider is used in the PLL feedback path to reduce the overall power consumption.
Relation: 93(2), pp.97-113
URI: http://ntour.ntou.edu.tw/handle/987654321/28368
Appears in Collections:[電機工程學系] 期刊論文

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