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Please use this identifier to cite or link to this item: http://ntour.ntou.edu.tw:8080/ir/handle/987654321/28012

Title: Parallel Implementation of Convolution Encoder for Software Defined Radio on DSP Architecture
Authors: Jui-Chieh Lin;Chu Yu;Mao-Hsu Yen;Pao-Ann Hsiung;Sao-Jie Chen;Yu Hen Hu
Contributors: NTOU:Department of Computer Science and Engineering
國立臺灣海洋大學:資訊工程學系
Keywords: 802.11a;Vector processing;convolutional encoder;software-defined radio
Date: 2009-07
Issue Date: 2011-10-21T02:35:07Z
Publisher: 2009 International Symposium on Systems, Architectures,MOdeling,and Simulation(SAMOS)
Abstract: Abstract:The question of how to efficiently implement bit-oriented operations such as convolutional encoding in a word-based processor platform is investigated. Our approach is to treat each word as a vector of individual bits. By reformulating a bit-oriented algorithm in vectorized format, it is shown in this work that significant speed-up of execution of such an algorithm can be achieved. Toward this goal, an efficient code generation design methodology is proposed to leverage the effort of common sub-expression elimination (CSE). The task of efficient vector-oriented code generation then becomes a pattern matching problem. The vectorization approach is demonstrated by the convolutional encoding portion of the IEEE 802.11a (WiFi) standard, implemented in C language on a Sandbridge Technologiescopy Inc. SB3010 baseband processor evaluation board, and more than 90% instruction cycle reduction is observed.
Relation: pp.180-186
URI: http://ntour.ntou.edu.tw/handle/987654321/28012
Appears in Collections:[資訊工程學系] 演講及研討會

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