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Please use this identifier to cite or link to this item: http://ntour.ntou.edu.tw:8080/ir/handle/987654321/18829

Title: 雙調變模式之同步高效率降壓穩壓器設計
A Dual-Mode Synchronous High Efficiency BUCK Converters
Authors: Ya-Wu Chung
鍾業武
Contributors: NTOU:Department of Electrical Engineering
國立臺灣海洋大學:電機工程學系
Keywords: 降壓穩壓器;停用時間;非重疊式;雙模
Buck converter;Deadtime;Non-Overlap;Dual-Mode
Date: 2010
Issue Date: 2011-07-04T01:04:31Z
Abstract: 本論文為一雙模調變的新型零電流偵測(ZCD) 和自動調整停用時間(DT)架構、此架構可以運用在直流對直流降壓切換式穩壓器/轉換器,在重載狀況下轉換器進入脈衝寬度調變模式,在輕載狀況下轉換器進入脈衝頻率調變模式,此架構操作在PWM與PFM皆具有非常高的功率轉換效率。且此架構無論是在PWM或是PFM皆可以精確的隨負載電流變化大小去設定在適當的DT範圍,避免P、N輸出功率電晶體短路或多餘的功率消耗,此架構可以提升以往在高負載電流轉換效率的問題,當在負載電流越大時,轉換效率比傳統架構還要好。因為在重載情況下新型電路可以自動調整DT 在適當範圍,而傳統的DT無法改變其範圍,此為自動調整DT的優點,如果當穩壓器操作在更高頻時,DT範圍佔整個週期的比例更大,可能影響效率更為嚴重,另外此架構可以避免PFM在低電流時,ZCD誤動作的發生。更特別的是此種架構不但只運用於降壓型穩壓器,如果再加以改良,也可以運用在昇壓型穩壓器、降昇壓穩壓器。本論文電路係以台積電0.35um 2P4M 5V polycide CMOS的製程設計,而輸入操作電壓的範圍為3V~5V之間,這架構最大的轉換效率在負載電流150mA可達到95.8%的高效率,在負載電流50mA~420mA之間運作時,轉換效率皆可達到具有94%以上的高效率。
This thesis is a new type of dual-mode modulation Zero Current Detection (ZCD) & Adaptive deadtime architecture that can be used in the DC to DC step-down switching voltage regulator/converter, heavy conditions in the converter into the pulse width modulation mode (PWM), in the light load conditions converter into the pulse frequency modulation (PFM), this structure operation in PWM and PFM are very high power conversion efficiency. And this structure both in PWM or PFM are accurate with the load current can change the size to set the appropriate Deadtime range, to avoid the P, N output transistor short-circuit or redundant power consumption, this architecture will break through the high-load current conversion efficiency would drop the issue, the conversion efficiency of this structure is greater than the conventional one’s in the high-load current. When the operating frequency is getting higher, the ratio of dead time per cycle is increased. It gets worse the conversion efficiency in conventional structure. Also this architecture can be avoided PFM at low currents, ZCD malfunction from happening. More specifically, such a structure does not only apply buck regulator, if any further improvement can also be used in step-up regulator, reducing step-up regulator. In this thesis, the chip is based on TSMC 0.35um 2P4M 5V polycide CMOS manufacturing process design, the input operating voltage range from 3V ~ 5V between this framework, the maximum conversion efficiency can be achieved in the load current 150mA ultra-high efficiency of 95.8% In between the load current 50mA ~ 420mA operation, the conversion efficiency can deliver more than 94% with a high efficiency of presenting
URI: http://ethesys.lib.ntou.edu.tw/cdrfb3/record/#G0T95430005
http://ntour.ntou.edu.tw/ir/handle/987654321/18829
Appears in Collections:[電機工程學系] 博碩士論文

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