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Please use this identifier to cite or link to this item: http://ntour.ntou.edu.tw:8080/ir/handle/987654321/18468

Title: 5.2GHz CMOS無線通訊發射端電路設計
Design of a 5.2GHz CMOS Transmitter for Wireless Communication
Authors: Hin-Jie Chen
陳宏傑
Contributors: NTOU:Department of Electrical Engineering
國立臺灣海洋大學:電機工程學系
Keywords: 高頻功率放大器;混頻器
rf power amplifier;mixer
Date: 2004
Issue Date: 2011-07-04
Abstract: 本論文為一個5.2GHz CMOS無線通訊發射端電路設計。此發射器包含功率放大器、正交升頻混頻器與正交壓控振盪器,設計是採用台積電0.18um 1P6M CMOS製程來實現。為了要得到足夠的功率以及效率,我們採用AB類的功率放大器,模擬結果顯示本功率放大器可以提供20.87dBm的輸出功率、21.45%的最大Power Added Efficiency;正交升頻混頻器提供2.01dB的轉換增益、2.3dBm的1dB壓縮點(P1dB)、12.4dBm的第三階交互調變截斷點(IP3);正交壓控振盪器有著436MHz調諧範圍、相位雜訊在距離振盪中心頻率1MHz為-105dBc。最後,射頻發射端的模擬特性為13.5dB的增益、-1.02dBm的1dB壓縮點、9.9dBm的第三階交互調變截斷點。整體發射器的消耗功率為478mW。
This thesis presents the design of a 5.2GHz CMOS transmitter circuit for wireless communication. This transmitter contains a power amplifier, a quadrature up conversion mixer and a quadrature voltage control oscillator (VCO). TSMC 0.18um CMOS process is used to implement the transmitter. For enough output power and good efficiency, we adopt a class AB power amplifier, simulation results show that the output power and maximum power added efficiency of power amplifier are 20.87dBm and 21.45%, respectively. Quadrature up conversion mixer provides 2.01dB conversion gain, 2.3dBm 1dB-compression point (P1dB), 12.4dBm third-order intermodulation intercept point (IP3).The quadrature VCO has 436MHz tuning range and –105dBc phase noise at 1MHz offset. The whole transmitter shows characteristics of 13.5dB conversion gain, -1.02dBm 1dB-compression point, and 9.9dBm IP3. The power consumption is 478mW.
URI: http://ethesys.lib.ntou.edu.tw/cdrfb3/record/#G0M92530052
http://ntour.ntou.edu.tw/ir/handle/987654321/18468
Appears in Collections:[電機工程學系] 博碩士論文

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