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Please use this identifier to cite or link to this item: http://ntour.ntou.edu.tw:8080/ir/handle/987654321/18320

Title: 5.2GHz CMOS射頻接收器之前級電路設計
Authors: HanChouHsu
許漢州
Contributors: NTOU:Department of Electrical Engineering
國立臺灣海洋大學:電機工程學系
Keywords: 5GHz CMOS 射頻接收器;低雜訊放大器;混波器;四相位壓控振盪器
Date: 2003
Issue Date: 2011-07-04
Abstract: 摘要 本論文以TSMC0.18 1P6M CMOS製程來研製應用於無線區域網路IEEE 802.11a規格之全積體化低中頻接收器之前級電路。在接收器的工作頻帶規劃上,射頻訊號為5.15GHz~5.35GHz,經4.95GHz~5.15GHz之本地振盪器訊號降至中頻200MHz 。本論文所研製的接收器前級電路包含了四個子電路:分別是單端低雜訊放大器、主動式雙端平衡式混波器、四相位輸出壓控振盪器、以及一個離散元件被動耦合器。其中離散元件被動式耦合器之作用為一單端轉差動電路。 在電路之模擬特性方面,低雜訊放大器之放大器增益為15.5dB、雜訊指數為2.4dB、輸入P1dB點為-14dBm,主動式雙端平衡混波器之轉換增益為10.94dB、雜訊指數為9.4dB、輸入P1dB點為-18dBm,四相位輸出振盪器之頻率可調範圍為4.920MHz~5242MHz,1MHz之相位雜訊為-105dBc/Hz,而離散元件被動式耦合器之損耗在5.2GHz時兩差動訊號之損耗分別為-6.2dB與-3.9dB。 最後,在整體接收器模擬特性方面,整個前級電路之轉換增益為29.6dB,整體接收器之雜訊指數為3.5dB,輸入P1dB為-36dBm,整個接收器消耗的功率為-32mW。
Abstract This thesis presents the development of a fully integrated low IF Receiver front end for IEEE 802.11a WLAN Standard by using TSMC 0.18μm 1p6m CMOS process. The RF input signal is from 5.15 to 5.35 GHz , the LO is from 4.95GHz to 5.15GHz ,and the IF is at 200MHz.The receiver font-end of this thesis includes four subcircuits which are a single ended LNA, an active double balance mixer, a qudrature VCO, and a single to differential circuit by using a lumped element passive hybrid. The LNA features the simulated results of 15-dB gain, 2.4-dB noise figure, and -14dBm input P1dB. The mixer exhibits 10.94-dB gain,9.4-dB noise figure,-18dBm input P1dB. The VCO has an output frequency from 4.920MHz~5242MHz with -105dBc/Hz @1 MHz phase noise .The loss of the differential output signals of the lumped element passive hybrid are -6.2-dB and -3.9-dB, respectively. Finally, the RF receiver front end shows the simulation results of 29.6-dB conversion gain, 3.5-dB noise figure, -36-dBm input P1dB and 32mW power dissipation.
URI: http://ethesys.lib.ntou.edu.tw/cdrfb3/record/#G0M91530038
http://ntour.ntou.edu.tw/ir/handle/987654321/18320
Appears in Collections:[電機工程學系] 博碩士論文

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