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Please use this identifier to cite or link to this item: http://ntour.ntou.edu.tw:8080/ir/handle/987654321/18306

Title: 1.8伏特的低壓降穩壓器之設計
1.8V Low Dropout Voltage Regulator Design
Authors: An-Koo Lai
賴安谷
Contributors: NTOU:Department of Electrical Engineering
國立臺灣海洋大學:電機工程學系
Keywords: 低壓降穩壓器
LDO;Regulator
Date: 2003
Issue Date: 2011-07-04
Abstract: 摘要:典型的PMOS元件或PNP電晶體之開回路增益,使用PMOS元件或PNP電晶體之LDO調節器具有三個重要的極點。主極點P(DOM)是由調節器的誤差放大器所決定。負載極點P(LOAD)是由輸出電容器以及負載所決定,因此會隨著負載電流的改變而改變。 傳輸元件極點P(PASS)則是由傳輸元件(pass element)之寄生電容值決定。對任何負回授的系統來說,系統穩定的條件為當相位為360°時(回授信號的180°加上誤差放大器反向輸入端的180°),系統的開回路增益必須低於0 dB。以另一種方法來說,系統的相位邊界值(phase margin)必須足夠(相位邊限是指當增益為0 dB時,系統距360°的相位差值)。由於每個極點可以貢獻90°的正相位移並造成20dB/decade (或 -1)下降率(rolloff)的增益改變,因此一個三個極點、高增益的系統必須加以補償方能達致穩定。 如果開回路增益曲線在通過0 dB之前的下降率是20dB/decade(此特性如同一單極點系統)的話,調節器就是無條件穩定的(有足夠的相位邊限)。最常用的補償方法為在系統中插入零點以抵銷極點產生的相位位移以及下降率的改變。由於LDO調節器在輸出端需要加上一輸出電容器方能正常動作,使用此電容器的ESR將是產生此一零點最簡單且廉價的方法。
ABSTRACT Choosing an output capacitor for LDO regulators with PNP or PMOS pass element can be difficult due to specific ESR requirements. This application note explains why higher ESR capacitors are necessary, how to choose them, and how to determine whether or not the regulator is stable. In the typical PMOS or PNP open loop gain plot , there are three important poles in a PMOS or PNP pass element based LDO regulator. The dominant pole, P(DOM), is set in the regulator’s error amplifier. The load pole, P(LOAD), is formed by the output capacitor and load and therefore varies with load current. The pass device pole, P(PASS), is formed by the parasitic capacitance of the pass element. In order for any negative feedback system to be stable, the open loop gain of the system must be below 0 dB when the phase is 360°(180°of the fed-back signal plus the 180°from the inverting input of the error amplifier). Stated another way, the system must have sufficient phase margin, i.e., the amount of phase shift remaining until 360° degree when the gain is at 0 dB. Since each pole contributes 90°of phase shift and 20dB/decade (or -1) rolloff in gain, a three-pole, high gain system requires compensation in order to be stable. A regulator is unconditionally stable (i.e., has sufficient phase margin) if the open loop gain curve rolls off at 20dB/decade (i.e., like a single pole system) before crosses 0 dB. The most common method of compensation is to insert a zero in the system to cancel the phase shift and rolloff of one of the poles. Since an LDO already requires an output capacitor for normal operation, using the output capacitor’s ESR is typically the simplest and least expensive method for generating this zero.
URI: http://ethesys.lib.ntou.edu.tw/cdrfb3/record/#G0M91530030
http://ntour.ntou.edu.tw/ir/handle/987654321/18306
Appears in Collections:[電機工程學系] 博碩士論文

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