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Title: RSA加解密晶片分析與設計
Implementation of RSA Encryption/Decryption Chip
Authors: 詹景裕;林銘波
Contributors: NTOU:Department of Computer Science and Engineering
Keywords: RSA演算法;Montgomery演算法;心脈式陣列;超高規模集成電路硬體描述語言
RSA algorithm;Montgomery algorithm;Systolic array;VHDL
Date: 2000-08
Issue Date: 2011-06-28T07:57:30Z
Publisher: 行政院國家科學委員會
Abstract: 摘要:本文設計與實作一個以RSA 演算法為基礎的512 位元公開金鑰密碼系統(Public KeyCryptosystem)加解密晶片,此晶片使用蒙哥馬利演算法(Montgomery Algorithm),簡化RSA 演算法中複雜的指數餘數運算﹔為有效降低晶片面積,採用心脈式陣列(Systolic Array)方式,設計主要運算單元:乘法與餘數運算電路。實作部分以FPGA 完成。本文所完成之512 位元RSA 加、解密晶片最高工作頻率為43.5 MHz,輸出鮑率為28.2 Kbps。
abstract:The role of cryptography is more important to prevent the computer- and communication-based crime in recent years. Many applications of cryptographic methods have been addressed recently from electronic mail, trading, and banking to network security. In this paper, the implementation of a 512 bits public key cryptosystem of RSA encryption/ decryption chip based on the Montgomery algorithm to simplify the complexity of exponential modular operation in RSA algorithm is presented. The architecture of chip includes two components: modular and multiplier. We implemented these two components based on the 257 bits pipelining systolic array to achieve a low die area. We applied the VHDL (VHSIC Hardware Description Language) to accomplish its design entry. This chip completed by using FPGA (Field Programmable Gate Array). Its clock rate can reach 43.5 MHz and the baud rate is 28.2 Kbits/sec.
Relation: NSC89-2213-E019-018
Appears in Collections:[Department of Computer Science and Engineering] Research Reports

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